floogen: Add NoC generation framework #24

fischeti · 2024-01-05T09:36:20Z

This PR adds a network generation framework called floogen

Added

NoC generation framework called floogen. Documentation can be foundin the docs folder.

Changed

the exported include folder of the floo package is moved to hw/include.
The LICENSE file was updated to reflect that the project uses the Solderpad Hardware License Version 2.1 for all hw files and the Apache License 2.0 for software related files.
The directory was restructured to accomodate the new floogen framework. The src was renamed to hw, which contains only SystemVerilog code. Test modules and testbenches were also moved to hw/test and hw/tb respectively. The same holds true for wave files, which are now located in hw/tb/wave.
The SV packages floo_axi_pkg and floo_narrow_wide_pkg are now generated by floogen. The configuration files were moved to the floogen/examples folder, and were aligned with the new floogen configuration format, that is written in YAML instead of hjson.
Reworked the python dependencies to use pyproject.toml instead of requirements.txt. Furthermore, the python requirement was bumped to 3.10 due to floogen (which makes heavy use of the newer match syntax)

Removed

axi_channel_compare was removed in favor of axi_chan_compare from the axi repository.
Removed flit generation script flit_gen.py including configuration files, since this is now integrated into floogen (in conjunction with the --only-pkg flag)

This is now integrated into floogen

github-actions · 2024-01-08T16:33:01Z

hw/floo_axi_chimney.sv

+    .RouteAlgo      ( RouteAlgo       ),
+    .UseIdTable     ( UseIdTable      ),
+    .XYAddrOffsetX  ( XYAddrOffsetX   ),
+    .XYAddrOffsetY  ( XYAddrOffsetY   ),
+    .IdAddrOffset   ( IdAddrOffset    ),
+    .NumIDs         ( AddrMapNumIDs   ),
+    .NumRules       ( AddrMapNumRules ),
+    .id_t           ( id_t            ),
+    .id_rule_t      ( addr_map_rule_t ),
+    .addr_t         ( axi_in_addr_t   )
  ) i_floo_narrow_route_comp [NumAddrDecoders-1:0] (
    .clk_i,
    .rst_ni,
-    .id_map_i,
+    .id_map_i   ( AddrMap         ),
    .addr_i     ( addr_to_decode  ),
    .id_o       ( decoded_id      )


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.RouteAlgo ( RouteAlgo ),

.UseIdTable ( UseIdTable ),

.XYAddrOffsetX ( XYAddrOffsetX ),

.XYAddrOffsetY ( XYAddrOffsetY ),

.IdAddrOffset ( IdAddrOffset ),

.NumIDs ( AddrMapNumIDs ),

.NumRules ( AddrMapNumRules ),

.id_t ( id_t ),

.id_rule_t ( addr_map_rule_t ),

.addr_t ( axi_in_addr_t )

) i_floo_narrow_route_comp [NumAddrDecoders-1:0] (

.clk_i,

.rst_ni,

.id_map_i,

.id_map_i ( AddrMap ),

.addr_i ( addr_to_decode ),

.id_o ( decoded_id )

.RouteAlgo (RouteAlgo),

.UseIdTable (UseIdTable),

.XYAddrOffsetX(XYAddrOffsetX),

.XYAddrOffsetY(XYAddrOffsetY),

.IdAddrOffset (IdAddrOffset),

.NumIDs (AddrMapNumIDs),

.NumRules (AddrMapNumRules),

.id_t (id_t),

.id_rule_t (addr_map_rule_t),

.addr_t (axi_in_addr_t)

) i_floo_narrow_route_comp[NumAddrDecoders-1:0] (

.clk_i,

.rst_ni,

.id_map_i(AddrMap),

.addr_i (addr_to_decode),

.id_o (decoded_id)

github-actions · 2024-01-08T16:33:02Z

hw/floo_narrow_wide_chimney.sv

+    .RouteAlgo      ( RouteAlgo       ),
+    .UseIdTable     ( UseIdTable      ),
+    .XYAddrOffsetX  ( XYAddrOffsetX   ),
+    .XYAddrOffsetY  ( XYAddrOffsetY   ),
+    .IdAddrOffset   ( IdAddrOffset    ),
+    .NumIDs         ( AddrMapNumIDs   ),
+    .NumRules       ( AddrMapNumRules ),
+    .id_t           ( id_t            ),
+    .id_rule_t      ( addr_map_rule_t ),
+    .addr_t         ( addr_t          )
  ) i_floo_narrow_route_comp [NumAddrDecoders-1:0] (
    .clk_i,
    .rst_ni,
-    .id_map_i,
+    .id_map_i   ( AddrMap         ),
    .addr_i     ( addr_to_decode  ),
    .id_o       ( decoded_id      )


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.RouteAlgo ( RouteAlgo ),

.UseIdTable ( UseIdTable ),

.XYAddrOffsetX ( XYAddrOffsetX ),

.XYAddrOffsetY ( XYAddrOffsetY ),

.IdAddrOffset ( IdAddrOffset ),

.NumIDs ( AddrMapNumIDs ),

.NumRules ( AddrMapNumRules ),

.id_t ( id_t ),

.id_rule_t ( addr_map_rule_t ),

.addr_t ( addr_t )

) i_floo_narrow_route_comp [NumAddrDecoders-1:0] (

.clk_i,

.rst_ni,

.id_map_i,

.id_map_i ( AddrMap ),

.addr_i ( addr_to_decode ),

.id_o ( decoded_id )

.RouteAlgo (RouteAlgo),

.UseIdTable (UseIdTable),

.XYAddrOffsetX(XYAddrOffsetX),

.XYAddrOffsetY(XYAddrOffsetY),

.IdAddrOffset (IdAddrOffset),

.NumIDs (AddrMapNumIDs),

.NumRules (AddrMapNumRules),

.id_t (id_t),

.id_rule_t (addr_map_rule_t),

.addr_t (addr_t)

) i_floo_narrow_route_comp[NumAddrDecoders-1:0] (

.clk_i,

.rst_ni,

.id_map_i(AddrMap),

.addr_i (addr_to_decode),

.id_o (decoded_id)

github-actions · 2024-01-09T08:08:26Z

hw/tb/tb_floo_axi_chimney.sv

    .AtopSupport        ( AtopSupport         ),
    .MaxAtomicTxns      ( 4                   ),
-    .RouteAlgo          ( floo_pkg::IdTable   ),
    .MaxTxns            ( MaxTxns             ),
    .MaxTxnsPerId       ( MaxTxnsPerId        ),
    .ReorderBufferSize  ( ReorderBufferSize   )


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.AtopSupport ( AtopSupport ),

.MaxAtomicTxns ( 4 ),

.RouteAlgo ( floo_pkg::IdTable ),

.MaxTxns ( MaxTxns ),

.MaxTxnsPerId ( MaxTxnsPerId ),

.ReorderBufferSize ( ReorderBufferSize )

.AtopSupport (AtopSupport),

.MaxAtomicTxns (4),

.MaxTxns (MaxTxns),

.MaxTxnsPerId (MaxTxnsPerId),

.ReorderBufferSize(ReorderBufferSize)

github-actions · 2024-01-09T08:08:26Z

hw/tb/tb_floo_axi_chimney.sv

    .AtopSupport        ( AtopSupport         ),
    .MaxAtomicTxns      ( 4                   ),
-    .RouteAlgo          ( floo_pkg::IdTable   ),
    .MaxTxns            ( MaxTxns             ),
    .MaxTxnsPerId       ( MaxTxnsPerId        ),
    .ReorderBufferSize  ( ReorderBufferSize   )


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.AtopSupport ( AtopSupport ),

.MaxAtomicTxns ( 4 ),

.RouteAlgo ( floo_pkg::IdTable ),

.MaxTxns ( MaxTxns ),

.MaxTxnsPerId ( MaxTxnsPerId ),

.ReorderBufferSize ( ReorderBufferSize )

.AtopSupport (AtopSupport),

.MaxAtomicTxns (4),

.MaxTxns (MaxTxns),

.MaxTxnsPerId (MaxTxnsPerId),

.ReorderBufferSize(ReorderBufferSize)

github-actions · 2024-01-09T08:08:26Z

hw/tb/tb_floo_rob.sv

    .MaxTxns            ( MaxTxns             ),
    .MaxTxnsPerId       ( MaxTxnsPerId        ),
-    .ReorderBufferSize  ( ReorderBufferSize   ),
-    .id_t               ( xy_id_t             )
+    .ReorderBufferSize  ( ReorderBufferSize   )


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.MaxTxns ( MaxTxns ),

.MaxTxnsPerId ( MaxTxnsPerId ),

.ReorderBufferSize ( ReorderBufferSize ),

.id_t ( xy_id_t )

.ReorderBufferSize ( ReorderBufferSize )

.MaxTxns (MaxTxns),

.MaxTxnsPerId (MaxTxnsPerId),

.ReorderBufferSize(ReorderBufferSize)

github-actions · 2024-01-09T08:08:26Z

hw/tb/tb_floo_rob.sv

      .MaxTxns            ( MaxTxns             ),
      .MaxTxnsPerId       ( MaxTxnsPerId        ),
-      .ReorderBufferSize  ( ReorderBufferSize   ),
-      .id_t               ( xy_id_t             )
+      .ReorderBufferSize  ( ReorderBufferSize   )


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.MaxTxns ( MaxTxns ),

.MaxTxnsPerId ( MaxTxnsPerId ),

.ReorderBufferSize ( ReorderBufferSize ),

.id_t ( xy_id_t )

.ReorderBufferSize ( ReorderBufferSize )

.MaxTxns (MaxTxns),

.MaxTxnsPerId (MaxTxnsPerId),

.ReorderBufferSize(ReorderBufferSize)

github-actions · 2024-01-09T08:29:38Z

hw/floo_axi_chimney.sv

+    .RouteAlgo      ( RouteAlgo       ),
+    .UseIdTable     ( UseIdTable      ),
+    .XYAddrOffsetX  ( XYAddrOffsetX   ),
+    .XYAddrOffsetY  ( XYAddrOffsetY   ),
+    .IdAddrOffset   ( IdAddrOffset    ),
+    .NumIDs         ( AddrMapNumIDs   ),
+    .NumRules       ( AddrMapNumRules ),
+    .AddrMap        ( AddrMap         ),
+    .id_t           ( id_t            ),
+    .id_rule_t      ( addr_map_rule_t ),
+    .addr_t         ( axi_in_addr_t   )
  ) i_floo_narrow_route_comp [NumAddrDecoders-1:0] (
    .clk_i,
    .rst_ni,
-    .id_map_i,
    .addr_i     ( addr_to_decode  ),
    .id_o       ( decoded_id      )


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.RouteAlgo ( RouteAlgo ),

.UseIdTable ( UseIdTable ),

.XYAddrOffsetX ( XYAddrOffsetX ),

.XYAddrOffsetY ( XYAddrOffsetY ),

.IdAddrOffset ( IdAddrOffset ),

.NumIDs ( AddrMapNumIDs ),

.NumRules ( AddrMapNumRules ),

.AddrMap ( AddrMap ),

.id_t ( id_t ),

.id_rule_t ( addr_map_rule_t ),

.addr_t ( axi_in_addr_t )

) i_floo_narrow_route_comp [NumAddrDecoders-1:0] (

.clk_i,

.rst_ni,

.id_map_i,

.addr_i ( addr_to_decode ),

.id_o ( decoded_id )

.RouteAlgo (RouteAlgo),

.UseIdTable (UseIdTable),

.XYAddrOffsetX(XYAddrOffsetX),

.XYAddrOffsetY(XYAddrOffsetY),

.IdAddrOffset (IdAddrOffset),

.NumIDs (AddrMapNumIDs),

.NumRules (AddrMapNumRules),

.AddrMap (AddrMap),

.id_t (id_t),

.id_rule_t (addr_map_rule_t),

.addr_t (axi_in_addr_t)

) i_floo_narrow_route_comp[NumAddrDecoders-1:0] (

.clk_i,

.rst_ni,

.addr_i(addr_to_decode),

.id_o (decoded_id)

github-actions · 2024-01-09T08:29:38Z

hw/floo_narrow_wide_chimney.sv

+    .RouteAlgo      ( RouteAlgo       ),
+    .UseIdTable     ( UseIdTable      ),
+    .XYAddrOffsetX  ( XYAddrOffsetX   ),
+    .XYAddrOffsetY  ( XYAddrOffsetY   ),
+    .IdAddrOffset   ( IdAddrOffset    ),
+    .NumIDs         ( AddrMapNumIDs   ),
+    .NumRules       ( AddrMapNumRules ),
+    .AddrMap        ( AddrMap         ),
+    .id_t           ( id_t            ),
+    .id_rule_t      ( addr_map_rule_t ),
+    .addr_t         ( addr_t          )
  ) i_floo_narrow_route_comp [NumAddrDecoders-1:0] (
    .clk_i,
    .rst_ni,
-    .id_map_i,
    .addr_i     ( addr_to_decode  ),
    .id_o       ( decoded_id      )


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.RouteAlgo ( RouteAlgo ),

.UseIdTable ( UseIdTable ),

.XYAddrOffsetX ( XYAddrOffsetX ),

.XYAddrOffsetY ( XYAddrOffsetY ),

.IdAddrOffset ( IdAddrOffset ),

.NumIDs ( AddrMapNumIDs ),

.NumRules ( AddrMapNumRules ),

.AddrMap ( AddrMap ),

.id_t ( id_t ),

.id_rule_t ( addr_map_rule_t ),

.addr_t ( addr_t )

) i_floo_narrow_route_comp [NumAddrDecoders-1:0] (

.clk_i,

.rst_ni,

.id_map_i,

.addr_i ( addr_to_decode ),

.id_o ( decoded_id )

.RouteAlgo (RouteAlgo),

.UseIdTable (UseIdTable),

.XYAddrOffsetX(XYAddrOffsetX),

.XYAddrOffsetY(XYAddrOffsetY),

.IdAddrOffset (IdAddrOffset),

.NumIDs (AddrMapNumIDs),

.NumRules (AddrMapNumRules),

.AddrMap (AddrMap),

.id_t (id_t),

.id_rule_t (addr_map_rule_t),

.addr_t (addr_t)

) i_floo_narrow_route_comp[NumAddrDecoders-1:0] (

.clk_i,

.rst_ni,

.addr_i(addr_to_decode),

.id_o (decoded_id)

github-actions · 2024-01-09T08:29:38Z

hw/floo_route_comp.sv

  input  logic  clk_i,
  input  logic  rst_ni,
  input  addr_t addr_i,
-  input  id_rule_t [NumRules-1:0] id_map_i,
  output id_t   id_o


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic clk_i,

input logic rst_ni,

input addr_t addr_i,

input id_rule_t [NumRules-1:0] id_map_i,

output id_t id_o

input logic clk_i,

input logic rst_ni,

input addr_t addr_i,

output id_t id_o

github-actions · 2024-01-09T08:29:38Z

hw/tb/tb_floo_axi_chimney.sv

+    .clk_i          ( clk             ),
+    .en_i           ( rst_n           ),
+    .end_of_sim_i   ( &end_of_sim     ),
+    .req_i          ( node_man_req[0] ),
+    .rsp_i          ( node_man_rsp[0] ),
+    .ar_in_flight_o (                 ),
+    .aw_in_flight_o (                 )


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.clk_i ( clk ),

.en_i ( rst_n ),

.end_of_sim_i ( &end_of_sim ),

.req_i ( node_man_req[0] ),

.rsp_i ( node_man_rsp[0] ),

.ar_in_flight_o ( ),

.aw_in_flight_o ( )

.clk_i (clk),

.en_i (rst_n),

.end_of_sim_i (&end_of_sim),

.req_i (node_man_req[0]),

.rsp_i (node_man_rsp[0]),

.ar_in_flight_o(),

.aw_in_flight_o()

github-actions · 2024-01-09T08:29:39Z

hw/test/axi_reorder_remap_compare.sv

        aw_w_queue_recv.push_back(aw_queue_sent[i][0]);
        // Remove from sent queue
-        aw_queue_sent[i].pop_front();
+        void'(aw_queue_sent[i].pop_front());
        match = 1;
        break;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

aw_w_queue_recv.push_back(aw_queue_sent[i][0]);

// Remove from sent queue

aw_queue_sent[i].pop_front();

void'(aw_queue_sent[i].pop_front());

match = 1;

break;

github-actions · 2024-01-09T08:29:38Z

hw/floo_axi_chimney.sv

+    .RouteAlgo      ( RouteAlgo       ),
+    .UseIdTable     ( UseIdTable      ),
+    .XYAddrOffsetX  ( XYAddrOffsetX   ),
+    .XYAddrOffsetY  ( XYAddrOffsetY   ),
+    .IdAddrOffset   ( IdAddrOffset    ),
+    .NumIDs         ( AddrMapNumIDs   ),
+    .NumRules       ( AddrMapNumRules ),
+    .AddrMap        ( AddrMap         ),
+    .id_t           ( id_t            ),
+    .id_rule_t      ( addr_map_rule_t ),
+    .addr_t         ( axi_in_addr_t   )
  ) i_floo_narrow_route_comp [NumAddrDecoders-1:0] (
    .clk_i,
    .rst_ni,
-    .id_map_i,
    .addr_i     ( addr_to_decode  ),
    .id_o       ( decoded_id      )


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.RouteAlgo ( RouteAlgo ),

.UseIdTable ( UseIdTable ),

.XYAddrOffsetX ( XYAddrOffsetX ),

.XYAddrOffsetY ( XYAddrOffsetY ),

.IdAddrOffset ( IdAddrOffset ),

.NumIDs ( AddrMapNumIDs ),

.NumRules ( AddrMapNumRules ),

.AddrMap ( AddrMap ),

.id_t ( id_t ),

.id_rule_t ( addr_map_rule_t ),

.addr_t ( axi_in_addr_t )

) i_floo_narrow_route_comp [NumAddrDecoders-1:0] (

.clk_i,

.rst_ni,

.id_map_i,

.addr_i ( addr_to_decode ),

.id_o ( decoded_id )

.RouteAlgo (RouteAlgo),

.UseIdTable (UseIdTable),

.XYAddrOffsetX(XYAddrOffsetX),

.XYAddrOffsetY(XYAddrOffsetY),

.IdAddrOffset (IdAddrOffset),

.NumIDs (AddrMapNumIDs),

.NumRules (AddrMapNumRules),

.AddrMap (AddrMap),

.id_t (id_t),

.id_rule_t (addr_map_rule_t),

.addr_t (axi_in_addr_t)

) i_floo_narrow_route_comp[NumAddrDecoders-1:0] (

.clk_i,

.rst_ni,

.addr_i(addr_to_decode),

.id_o (decoded_id)

github-actions · 2024-01-09T08:29:38Z

hw/floo_narrow_wide_chimney.sv

+    .RouteAlgo      ( RouteAlgo       ),
+    .UseIdTable     ( UseIdTable      ),
+    .XYAddrOffsetX  ( XYAddrOffsetX   ),
+    .XYAddrOffsetY  ( XYAddrOffsetY   ),
+    .IdAddrOffset   ( IdAddrOffset    ),
+    .NumIDs         ( AddrMapNumIDs   ),
+    .NumRules       ( AddrMapNumRules ),
+    .AddrMap        ( AddrMap         ),
+    .id_t           ( id_t            ),
+    .id_rule_t      ( addr_map_rule_t ),
+    .addr_t         ( addr_t          )
  ) i_floo_narrow_route_comp [NumAddrDecoders-1:0] (
    .clk_i,
    .rst_ni,
-    .id_map_i,
    .addr_i     ( addr_to_decode  ),
    .id_o       ( decoded_id      )


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.RouteAlgo ( RouteAlgo ),

.UseIdTable ( UseIdTable ),

.XYAddrOffsetX ( XYAddrOffsetX ),

.XYAddrOffsetY ( XYAddrOffsetY ),

.IdAddrOffset ( IdAddrOffset ),

.NumIDs ( AddrMapNumIDs ),

.NumRules ( AddrMapNumRules ),

.AddrMap ( AddrMap ),

.id_t ( id_t ),

.id_rule_t ( addr_map_rule_t ),

.addr_t ( addr_t )

) i_floo_narrow_route_comp [NumAddrDecoders-1:0] (

.clk_i,

.rst_ni,

.id_map_i,

.addr_i ( addr_to_decode ),

.id_o ( decoded_id )

.RouteAlgo (RouteAlgo),

.UseIdTable (UseIdTable),

.XYAddrOffsetX(XYAddrOffsetX),

.XYAddrOffsetY(XYAddrOffsetY),

.IdAddrOffset (IdAddrOffset),

.NumIDs (AddrMapNumIDs),

.NumRules (AddrMapNumRules),

.AddrMap (AddrMap),

.id_t (id_t),

.id_rule_t (addr_map_rule_t),

.addr_t (addr_t)

) i_floo_narrow_route_comp[NumAddrDecoders-1:0] (

.clk_i,

.rst_ni,

.addr_i(addr_to_decode),

.id_o (decoded_id)

github-actions · 2024-01-09T08:29:38Z

hw/floo_route_comp.sv

  input  logic  clk_i,
  input  logic  rst_ni,
  input  addr_t addr_i,
-  input  id_rule_t [NumRules-1:0] id_map_i,
  output id_t   id_o


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic clk_i,

input logic rst_ni,

input addr_t addr_i,

input id_rule_t [NumRules-1:0] id_map_i,

output id_t id_o

input logic clk_i,

input logic rst_ni,

input addr_t addr_i,

output id_t id_o

github-actions · 2024-01-09T08:29:39Z

hw/tb/tb_floo_axi_chimney.sv

+    .clk_i          ( clk             ),
+    .en_i           ( rst_n           ),
+    .end_of_sim_i   ( &end_of_sim     ),
+    .req_i          ( node_man_req[0] ),
+    .rsp_i          ( node_man_rsp[0] ),
+    .ar_in_flight_o (                 ),
+    .aw_in_flight_o (                 )


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.clk_i ( clk ),

.en_i ( rst_n ),

.end_of_sim_i ( &end_of_sim ),

.req_i ( node_man_req[0] ),

.rsp_i ( node_man_rsp[0] ),

.ar_in_flight_o ( ),

.aw_in_flight_o ( )

.clk_i (clk),

.en_i (rst_n),

.end_of_sim_i (&end_of_sim),

.req_i (node_man_req[0]),

.rsp_i (node_man_rsp[0]),

.ar_in_flight_o(),

.aw_in_flight_o()

github-actions · 2024-01-09T08:29:39Z

hw/test/axi_reorder_remap_compare.sv

        aw_w_queue_recv.push_back(aw_queue_sent[i][0]);
        // Remove from sent queue
-        aw_queue_sent[i].pop_front();
+        void'(aw_queue_sent[i].pop_front());
        match = 1;
        break;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

aw_w_queue_recv.push_back(aw_queue_sent[i][0]);

// Remove from sent queue

aw_queue_sent[i].pop_front();

void'(aw_queue_sent[i].pop_front());

match = 1;

break;

github-actions · 2024-01-09T08:40:48Z

hw/tb/tb_floo_dma_mesh.sv

        .NarrowMaxTxns            ( NarrowMaxTxns           ),
        .WideMaxTxns              ( WideMaxTxns             ),
        .NarrowReorderBufferSize  ( NarrowReorderBufferSize ),
        .WideReorderBufferSize    ( WideReorderBufferSize   ),
        .CutAx                    ( CutAx                   ),
-        .CutRsp                   ( CutRsp                  ),
-        .id_t                     ( xy_id_t                 )
+        .CutRsp                   ( CutRsp                  )


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.NarrowMaxTxns ( NarrowMaxTxns ),

.WideMaxTxns ( WideMaxTxns ),

.NarrowReorderBufferSize ( NarrowReorderBufferSize ),

.WideReorderBufferSize ( WideReorderBufferSize ),

.CutAx ( CutAx ),

.CutRsp ( CutRsp ),

.id_t ( xy_id_t )

.CutRsp ( CutRsp )

.NarrowMaxTxns (NarrowMaxTxns),

.WideMaxTxns (WideMaxTxns),

.NarrowReorderBufferSize(NarrowReorderBufferSize),

.WideReorderBufferSize (WideReorderBufferSize),

.CutAx (CutAx),

.CutRsp (CutRsp)

github-actions · 2024-01-09T08:51:41Z

hw/tb/tb_floo_rob.sv

-  xy_id_t [NumDirections-1:0] xy_id;
-  assign xy_id[Eject] = '{x: 2'd1, y: 2'd1};
+  id_t [NumDirections-1:0] xy_id;
+  assign xy_id[Eject] = '{x: 3'd1, y: 3'd1};

  typedef struct packed {
    int unsigned             idx;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

int unsigned idx;

int unsigned idx;

fischeti added 30 commits January 3, 2024 15:42

refactor: Rename src folder to hw

c394a22

refactor: Move testbenches into hw/tb

2bef31d

refactor: Move test modules into hw/test folder

1be7787

refactor: Create new hw/tb/wave directory for all wave scripts

bfc929e

refactor: Move typedef.svh in hw/include folder

dee6f1a

refactor: Modify Bender.yml accordingly

67d3694

refactor: Change paths in Makefile

2893672

refactor: Update fusesoc.core

205b46b

refactor: Update links in README

daabf1a

refactor: fix directory of test/include folder in Bender.yml

7748e2d

refactor: Fix more include folders

e0a153a

refactor: Fix more paths

2d98d27

floogen: Copy in repository

b88a4d2

license: Update license headers in python and YAML files

f91d30b

ci: Add pylint

ace071e

ci: Install floogen as package before linting

c41c489

py: Build only floogen package

b826a56

ci: Install pylint before linting

ba67660

py: Add click as python dependency

9005c5e

py: Update Homepage in pyproject.toml

7257365

py: Lint python files

7857c72

py: add jsonref as python dependency

a0e2e6b

py: Ignore similar python code lint warning for now

c11a053

jobs: Minor fix to pass CI

1d66d73

ci: Remove Whitespace

f553569

ci: Add NoC generation to CI

0ce9a1c

ci: Try to execute floogen as executable

6628908

ci: Write output to SV files

0f82457

ci: Format and upload the specific file

1ca27e4

ci: Lint generated SV files

4d428f4

util(flitgen)!: Remove previous flitgen script and config files

b142632

This is now integrated into floogen

github-actions bot reviewed Jan 8, 2024

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github-actions bot reviewed Jan 9, 2024

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fischeti added 4 commits January 9, 2024 09:39

hw(tb): Remove parameters from chimney instances that were removed

aabffb6

hw(chimney): Define Address Map as parameter instead of input

cbb8fc8

hw(tb): Fix missing signal in BW monitor

ccbf202

hw(test): Add void casts to get rid of warnings

e280161

fischeti force-pushed the floogen-integration branch from feb01ed to e280161 Compare January 9, 2024 08:39

github-actions bot reviewed Jan 9, 2024

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fischeti added 2 commits January 9, 2024 09:41

hw(tb): Remove xy_id_t typedefs

53c5e22

hw(pkg): Align coordinate dimensions in rob testbench

2abe86c

github-actions bot reviewed Jan 9, 2024

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fischeti added 7 commits January 9, 2024 11:18

doc: Update README with information about floogen

12b249d

doc: Move around sections in README

cfb8279

doc: Try to fix the generation link in the README

ff8d64d

floogen(vis): Fix visualization feature

b3e661c

doc: Update required python version in README

bb8b778

doc: Update the CHANGELOG

19780ed

doc: Add floogen documentation

cf58e50

fischeti marked this pull request as ready for review January 9, 2024 12:50

doc: Small fix in CHANGELOG

f8fb12d

fischeti changed the title ~~floogen~~ floogen: Add NoC generation framework Jan 9, 2024

fischeti added 2 commits January 9, 2024 14:00

doc: Add route_comp module in README

0ab002d

doc: Move both licenses to the root directory

7144d83

fischeti force-pushed the floogen-integration branch from 9595165 to 7144d83 Compare January 9, 2024 16:54

make: Bump QuestaSim default version

de16e9d

fischeti merged commit e0b7a5e into main Jan 9, 2024
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fischeti deleted the floogen-integration branch January 9, 2024 17:05

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floogen: Add NoC generation framework #24

floogen: Add NoC generation framework #24

fischeti commented Jan 5, 2024 •

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floogen: Add NoC generation framework #24

floogen: Add NoC generation framework #24

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fischeti commented Jan 5, 2024 • edited Loading

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fischeti commented Jan 5, 2024 •

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